| 摘要 |
The present invention provides a data processing apparatus comprising a processor core for generating addresses identifying locations in a memory and data values for storing in the memory, and a write buffer for storing the addresses and data values output by the processor core, and for subsequently outputting said addresses and data values to cause the data values to be stored in said memory. The write buffer comprises a plurality of rows, each row being arranged to store an address or data value and each row having associated therewith a flag field settable to indicate which of address or data values that row contains. In accordance with the present invention, the write buffer provided by the data processing apparatus adaptively adjusts the number of rows it requires for addresses, and hence can be arranged to occupy a relatively small area, whilst still efficiently supporting both burst mode and non-burst mode write traffic. |
