| 摘要 |
<p>A phase detecting/collating circuit (201) collates a phase of a reception serial data (302) input from outside through an external interface circuit (102), a phase of the reception data shift clock (306) output from the clock frequency divider/corrector circuit (202), and a phase of a phase collating clock (308) obtained by delaying the reception data shift clock (306) by 1/4 periodic cycle of the reception data shift clock by means of the delay circuit (203). By the phase collation in the phase detecting/collating circuit (201), if a difference in phase capable of generating a reception error in the data transmission circuit (101) is detected, the clock shortening timing signal (402) or the clock elongating timing signal (403) is output. A reception clock frequency divider/corrector circuit (202) corrects such as to shorten or elongate said reception data shift clock (306) when a clock shortening timing signal (402) or a clock elongating timing signal (403) is input, respectively. With this effect, the reception operation in the data transmission circuit is executed always normally. <IMAGE></p> |
