| 摘要 |
<p>A system for the serial-to-parallel conversion of binary data comprises a random access memory (RAM) 10 into which parallel data bits are written, and from which parallel data bits are read, with a word width of N bits, at least N-1 bit stores S0-S7 connected by an N-bit wide read/write data bus 14 to the RAM. In order to convert each N consecutive bits of a serial input data stream 16, an N-bit data word is repeatedly read from the RAM to the bit stores and written from the bit stores back to the RAM in synchronism with the serial input bits. Each time the word is read out and before it is written back, the then current serial input bit is substituted for a different one of the bits of word. Thus, after N such read/write operations the N-bit word written back to the RAM 10 corresponds to the N consecutive bits of the input data stream 16. The system may be modified to provide parallel-to-serial conversion (not shown) and multiplexed conversion of plural signal channels (Fig 4), e.g. for S-DIF audio signals,</p> |
