| 摘要 |
An in-circuit emulator (ICE) 1 for supporting debugging of a system which includes a processor has an internal trace memory 14 and a bit-width convertor 15. The internal trace memory 14 is embedded in an ICE CPU 2 and stores CPU internal signals fed from an emulator CPU core 11 that executes the same operations as a CPU (not shown) of the system to be debugged. The bit-width convertor 15 converts a CPU internal signal, read out of the internal trace memory 14, into a plurality of reduced bit-width signals, and supplies them to an ICE controller 4 outside the ICE CPU chip in multiple cycles. This configuration removes the restriction imposed (by the number of terminals of the ICE CPU chip 2) on the number of bits of the CPU internal signal which can be output in parallel, and overcomes the difficulty involved in sampling the internal CPU signals by the trace memory even as the operation frequency of the ICE CPU increases. |
