DRAM cell array with vertical transistors and process of manufacture

摘要

The DRAM cell arrangement has a semiconductor substrate (1) with projections (V) arranged in rows and columns. Adjacent rows of projections are arranged with translational symmetry to each other with respect to a y axis running parallel to the columns. One of the projections has at least a first source/drain region and under that a channel region of a selector transistor. The projection is provided with a gate dielectric at least in the region of the channel region. The projection with the gate dielectric is surrounded by a ring gate electrode (Ga) of the transistor. Adjacent gate electrodes along an x axis parallel to the rows are separated from each other and form a word line. The second source/drain regions of the transistors are etched into the substrate. The first source/drain region is electrically connected to a first capacitor electrode of a storage capacitor. A second electrode of the capacitor is separated from the first electrode by a capacitor dielectric. The second electrode is electrically connected to a bit line parallel to the y axis.