| 摘要 |
A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline. In some embodiments, one set of wordline drivers (positioned along one side of the array) drives the even-numbered wordlines, another set of wordline drivers (positioned along the opposite side of the array) drives the odd-numbered wordlines, and the system exchanges the bitline addresses of the first packet and last packet (or the first N bytes of the first packet and the last N bytes of the last packet) of each sector to be written to cells along an even-numbered wordline (or inverts the bitline addresses for the entire sector), but the system does not modify the bitline address of any of data bit to be written to cells connected along an odd-numbered wordline. Preferably, the system is operable in either a first mode in which it modifies the addresses to which data is to be written to a cell array (to reduce the time needed to read the data after it has been written) or a second mode in which it does not modify the addresses to which the data is to be written to the array.
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