| 摘要 |
An address transition detection circuit includes an address input unit; a first latch unit for latching an input address signal and activating an address transition detection signal; a second latch unit for latching an input level of the first latch unit at a first value in accordance with an output from the first latch unit while the address transition detection signal ATD is active; first and second delay units for delaying an output from the first latch unit; and a CMOS flip-flop for outputting the address transition detection signal having a predetermined width in accordance with outputs from the first latch unit and the first and second delay units.
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