| 摘要 |
PROBLEM TO BE SOLVED: To simplify a process of manufacturing a capacitor of three- dimensional structure and to enable a DRAM cell to be lessened in manufacturing cost and improved in manufacturing yield, by a method wherein a first conductivity-type purge region is provided to a semiconductor layer so as to purge minority carriers induced on an interface between the semiconductor layer and an insulating film. SOLUTION: A DRAM cell includes a MOSFET which is equipped with a gate 503 formed on the one surface of a P-type silicon layer 501 through the intermediary of a gate insulating film 502 and source/drain regions 504 and 505 doped with N<+> impurities and formed in the silicon layer 501 so as to form a channel region in the silicon layer 501. A plate electrode conductive layer 508 formed on the other side of the silicon layer 501 through the intermediary of an insulating film 506 is included. Moreover, a part of the silicon layer 501 under the source region 50 is doped with P<+> impurities to turn to a purge region 507, which is provided to purge minority carriers generated on an interface between the silicon layer 501 and the insulating film 506. |
