| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock synchronization delay control circuit, capable of widening an operation frequency band by switching the delay amount of the delay line of respective parts of the circuit. SOLUTION: Pluses START from a delay monitor 5 propagate through a delay line 6 for advancing pulses. After the same time as the time of propagating the pulses START through the delay line 6 has elapsed, pulses are outputted from a delay line 7 for retreating pulses and outputted through a pulse width restoration circuit 8 and a clock deliverer 9 as an internal clock INTCLK. A pulse detection circuit 13 detects whether or not the pulses START have propagated to an N stage. When the pulses START have propagated to the N stage, the pulse detection circuit 13 outputs detection signals Dctl for setting the delay time of a receiver 2, of a pulse generation circuit 3, of the delay monitor 5, of the pulse width restoration circuit 8 and of the clock deliverer 9 for a low frequency. As a result, the frequency band is widened. |
