Pulse wordline control circuit and method for a computer memory device

摘要

A PWL control circuit and method is provided for use on a memory device to control the high/low logic state of the wordlines connected to the memory cell array of the memory device during access operation. The memory device can be a DRAM (dynamic random-access memory) device or an SRAM (static random-access memory device). The PWL control circuit and method utilizes a feedback signal from the sense amplifier to control the high/low logic state of the wordlines of the memory device. This feature can help eliminate the problem of an early deactivation of the currently activated wordlines during access operation that would otherwise occur when using the RC delay circuit in the prior art. Therefore, even if process parameters of the memory device are changed, the reliable sensing of the data from the memory cells is not affected.