| 摘要 |
An electrostatic discharge (ESD) protection circuit for an IC device including a triple-well SCR and a control circuit connected between the triple-well SCR and ground. The triple-well SCR is implemented using triple-well CMOS technology to facilitate connection of the control circuit by isolating both terminals of the triple-well SCR from ground. The control circuit includes a switch circuit, a capacitor, or a combination thereof, for controlling the holding voltage of the triple-well SCR. The switch circuit is closed during non-operation (i.e., before power is applied to the IC device protected by the SCR) so that electrostatic discharge (ESD) energy is transmitted to ground through the triple-well SCR. Similarly, the capacitor transmits ESD pulses to ground during ESD events. During normal operation of the IC device, the switch circuit is controlled by system voltage to remain open. In contrast, the capacitor is charged when a voltage pulse triggers the triple-well SCR during normal IC operation, thereby reliably switching off the triple-well SCR by decreasing the voltage across the SCR below the holding voltage.
|
