发明名称 |
Dual clocking scheme in a multi-port RAM |
摘要 |
A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.
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申请公布号 |
US5959937(A) |
申请公布日期 |
1999.09.28 |
申请号 |
US19980024559 |
申请日期 |
1998.02.17 |
申请人 |
MITSUBISHI SEMICONDUCTOR AMERICA, INC. |
发明人 |
RANDOLPH, WILLIAM L.;CASSADA, RHONDA;LAO, TIM |
分类号 |
G06F12/08;G11C7/10;G11C7/22;G11C8/08;G11C8/12;G11C8/16;G11C11/00;(IPC1-7):G11C8/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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