| 摘要 |
PURPOSE: An edge detector is provided to reduce the size of the edge detector by detecting a change point of an input signal through the logic combination of the input signal, an inversed signal of the input signal, and a delay signal of the input signal. CONSTITUTION: An edge detector comprises a time delay unit(11) for delaying an input signal(ADD) for a predetermined time; an inverter(12) for inversing the input signal; and a logic combination unit(13) for taking, as an input, the input signal, an output signal from the time delay unit, and an output signal from the inverter, detecting a change point of the input signal, and outputting a result signal. The logic combination unit includes a first input terminal(a11) for receiving the input signal; a second input terminal(b11) for receiving the output signal from the time delay unit; a third input terminal(c11) for receiving the output signal from the inverter; a first transistor(Q1) connected between the first input terminal and an output terminal(OUT), wherein the first transistor has a gate connected to the second input terminal; a fourth transistor(Q4) connected between the third input terminal and the output terminal, wherein the fourth transistor has a gate connected to the second input terminal; and a second transistor(Q2) and a third transistor(Q3) connected in parallel between the second input terminal and the output terminal, wherein the second and third transistors have gates connected to the first input terminal and the third input terminal, respectively.
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