| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a circuit for storing data in a dynamic random access memory(DRAM) during the period of a reset state. SOLUTION: When an external reset signal EXRST received by a reset unit 6 is asserted, an internal reset signal INRST is generated by synchronizing the signal EXRST with an internal clock and impresses the signal INRST to a CPU 4 and other modules in the circuit to reset those. During the impression of the signal INRST to the CPU 4, the rate of a refresh signal generated by a DRAM controller 7 is raised in order to refresh data stored in the DRAM 3. When the signal EXRST is disabled, a delay reset signal DLYRST is generated and impressed to the controller 7 to reset the controller 7. Since the CPU 4 has been already reset, the controller 7 is immediately reconstituted and enabled again so as to restart the refresh of the DRAM 3 so that the data in the DRAM 3 can be maintained.</p> |
