发明名称
摘要 <p>PROBLEM TO BE SOLVED: To make a noise margin at the time of a normal reabout larger by setting a switching transistor in a nonconductive state at the time of a verification of the reading of data to set a data detecting reference at the time of the verification more strict. SOLUTION: In an EPROM, the detection output S of a high voltage detection circuit 6 is inverted by an inverter circuit 41 and the output of the circuit 41 is applied to the gate of the switching transistor 8b insertingly connected in between the 4a2 of one side of divided load transistors 4a1, 4a2 and a power source node 9. Consequently, since the number of operations of bit line load transistors is made smaller as compares with a normal reading time to lower a potential reading memory cells, the data detecting references made to become more strict.</p>
申请公布号 JP2954079(B2) 申请公布日期 1999.09.27
申请号 JP19970101302 申请日期 1997.04.18
申请人 TOSHIBA KK;TOSHIBA MAIKURO EREKUTORONIKUSU KK 发明人 IWAHASHI HIROSHI;MINAGAWA EISHIN
分类号 G11C16/02;G11C16/06;(IPC1-7):G11C16/06 主分类号 G11C16/02
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