| 摘要 |
The present invention provides antifuses that enhance the efficiency of a field programmable gate array and that decrease chip size. The antifuses comprise a plurality of first conductive layers formed on a substrate, an antifuse layer formed on a plurality of the first conductive layers, and a second conductive layer formed on the antifuse layer. A method of fabricating the antifuses comprises the steps of forming a plurality of first conductive layers on predetermined portions of a substrate, forming an insulating layer over the surface of the substrate, selectively etching the insulating layer to form a via hole that is connected with a plurality of the first conductive layers, forming an antifuse layer on a predetermined portion of the insulating layer, including the via hole, and forming a second conductive layer on a predetermined portion of the insulating layer, including the antifuse layer. |
