发明名称 METHOD FOR REJECTION TESTS OF LAYOUT-BEARING INSULATION OR SEMICONDUCTOR SUBSTRATE AND ELECTRONIC DEVICES FOR EXTERNAL EFFECTS
摘要 FIELD: DC and ac rejection tests of substrates of all kinds. SUBSTANCE: method involves measurement of electrophysical parameters of substrates under test with their circuit components connected as at least one two-terminal device during and/or after effect of external factors followed by comparing values obtained with similar parameters of standard and rejection of substrates not complying with specified data; two-terminal device is formed by separating two insulated power buses a on substrate, electrically combining remaining electric circuits into (n-2) buses, and interconnecting conglomerates of electric buses a, ,...(n-2) obtained. EFFECT: reduced labor consumption, improved reliability, and proximate evaluation of yield. 13 cl, 3 dwg
申请公布号 RU2138830(C1) 申请公布日期 1999.09.27
申请号 RU19980118271 申请日期 1998.10.09
申请人 ZAKRYTOE AKTSIONERNOE OBSHCHESTVO NAUCHNO-TEKHNICH 发明人 BORISOV JU.I.;GROSHEV A.S.;JUDIN B.N.;JAFRAKOV M.F.
分类号 G01R31/28;H01L21/66;H05K1/00 主分类号 G01R31/28
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