发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To optimize the impurity concentration of wells in a well isolation region, and the impurity concentration of normal wells in a semiconductor integrated circuit device having a well isolation structure. SOLUTION: Buried n-type wells 3a and 3b are respectively provided in a well isolation region and a second well region, shallow p-type wells 4a and 4b of an impurity concentration set independently of the n-type wells 3a and 3b are respectively provided directly over the wells 3a and 3b in a self alignment manner and the shallow well 4a in the well isolation region is encircled with shallow n-type wells 5a formed on the side surface sides of the well 4a in a state that the well 4a is connected electrically with the n-type well 3a is separated electrically from a semiconductor substrate 1. |
申请公布号 |
JPH11261022(A) |
申请公布日期 |
1999.09.24 |
申请号 |
JP19980065657 |
申请日期 |
1998.03.16 |
申请人 |
HITACHI LTD |
发明人 |
TANIGUCHI YASUHIRO;YADORI SHOJI;KURODA KENICHI;IKEDA SHUJI;HASHIMOTO KOJI |
分类号 |
H01L21/8247;H01L21/761;H01L21/8234;H01L21/8242;H01L27/088;H01L27/10;H01L27/108;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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