| 摘要 |
PROBLEM TO BE SOLVED: To optimize the impurity concentration of wells in a well isolation region and the impurity concentration of normal wells without causing an increase in production processes in a semiconductor integrated circuit device having a well isolation structure. SOLUTION: A photoresist pattern, through which a well isolation region and a second well, region are exposed, is formed on a semiconductor substrate 1 and thereafter, impurities are introduced in the substrate 1 by using this Photoresist pattern as a mask to form buried n-type wells 3a and 3b and impurities are introduced in the substrate using the same photoresist pattern as a mask to form shallow p-type wells 4a and 4b on the wells 3a and 3b in a self- alignment manner. Subsequently, after the photoresist pattern is removed, a photoresist pattern, through which the outer peripheral regions of the well isolation region and a third well region are exposed, is formed on the main surface of the substrate and thereafter, impurities are introduced in the substrate using this photoresist pattern as a mask to form shallow p-type wells 5a and a shallow n-type well 5b. |
