| 摘要 |
PROBLEM TO BE SOLVED: To prevent a sampling failure due to phase deviation of a clock, etc., and also to reduce power consumption. SOLUTION: In this circuit, a majority circuit DEC to which plural phase difference information up signal and dn signal are inputted from plural comparators TIPD, takes majority, corrects the phase difference information of a smaller number side to match the phase difference information of a larger number side to output. A lock state detection circuit LDEC detects a lock state of each phase comparator TIPD by means of the phase difference information and a switch circuit SW fixes a clock supplied to a selected phase comparator TIPD to a high level at the time of detecting the lock states of all of the comparators TIPD. When it is in a lock state, clocks are not inputted to the selected phase comparator and a phase comparison operation is stopped. |
