| 摘要 |
PROBLEM TO BE SOLVED: To attain a high speed clock by reducing the number of parts and adjusting a clock skew. SOLUTION: An input clock signal CLK2 is inputted to the waveform input terminal 21 of a potential comparing part 20. A variable potential part 30 generates variable potential Vth from its potential output terminal 33. The potential Vth is supplied to a comparing potential input terminal 22 of the comparing part 20 as comparing potential. Consequently the comparing part 20 outputs an output clock signal CLK0 obtained by adjusting a clock skew from its waveform output terminal 23. Thus the high speed clock can be attained. |
