发明名称 METHOD AND APPARATUS FOR CLOCK TIMING RECOVERY IN ψDSL, PARTICULARLY VDSL MODEMS
摘要 <p>Method and modem for fast timing recovery of transmitted data between a master ψDSL modem and a slave ψDSL modem, over a noisy, high loss, high distortion wiring. Transmitted QAM symbols are received and sampled (10) at the slave modem. The sampled data is split into in-phase (I) and quadrature (Q) channels (11, 12), each of which is filtered by matched filter (13, 14). The filtered I and Q outputs are sampled at twice the symbol rate and the lower and upper band edge components are extracted by modulating each of the sampled sequence of I and Q outputs with two discrete time sequences: cos(0.5πn) = ...,1,0,-1,0,... and sin(0.5πn) = ...,0,1,0,-1,... Each of the resulting products is filtered with a first order low-pass filter (26, 27) and re-sampled again at the symbol rate. The Bit Error Rate is computed (28), and the slave modem switches from blind timing recovery mode, to data directed timing recovery mode, after the Bit Error Rate has sufficiently decreased.</p>
申请公布号 WO1999048219(A1) 申请公布日期 1999.09.23
申请号 IL1999000154 申请日期 1999.03.18
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