| 摘要 |
The card includes two independent units of respectively an analog multiplexer (2a, 2b) and a coupled video decoder (3a, 3b), a digital multiplexer (4), a FIFO memory (5), and two clock generators (7) for a control of a synchronous timing generator (6). A compression chip set (8) is provided for receiving parts of the data stream from the FIFO memory and remaining parts from the synchronous timing generator. The card includes two independent units of respectively an analog multiplexer (2a, 2b) and a coupled video decoder (3a, 3b). A digital multiplexer (4) is provided for forwarding asynchronous brightness-, color-, and timing information from one of the units to a FIFO memory (5) as well as parallel to a synchronous timing generator (6). Two clock generators (7) are provided for the control of the synchronous timing generator. A compression chip set (8) is provided for receiving parts of the data stream from the FIFO memory and remaining parts from the synchronous timing generator. A bus component is provided for transmitting parameters to the components of the card, and for reading data from the compression chip set. |
