SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA

摘要

A SRAM bus architecture includes pass-through interconnect conductors (36). Each of the pass-through interconnect conductors (36) is connected to routing channels of the general interconnect architecture of the FPGA (10) through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistor and tri-state buffers are controlled by configurable SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements (38) to the address, data and control signal lines of the SRAM blocks (12), while other pass through the SRAM blocks (12) without being further connected to the SRAM bussing architecture.