| 摘要 |
<p>A contents addressable memory circuit includes an inputting section (12), a contents addressable memory section (CAM1, CAM2, CAMn) and a control section (7, 8, 9, 67, 68). The inputting section divides an input data into n (n is an integer equal to or larger than 2) data blocks and supplies the n data blocks and an input address. The contents addressable memory section performs a data retrieving operation in units of data blocks to output addresses and coincidence flags corresponding to the data blocks. The coincidence flag is indicative of whether there is a data coincident with the corresponding data block. The control section outputs one of the outputted addresses based on the outputted addresses and the coincidence flags. <IMAGE></p> |
