发明名称 |
Synchronous semiconductor memory device with multi-bank configuration |
摘要 |
Memory blocks provided to share a sense amplifier bank, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connected-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.
|
申请公布号 |
US5956285(A) |
申请公布日期 |
1999.09.21 |
申请号 |
US19970798953 |
申请日期 |
1997.02.11 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
WATANABE, NAOYA;DOSAKA, KATSUMI |
分类号 |
G11C11/407;G11C7/10;G11C8/16;G11C11/401;G11C11/409;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|