| 摘要 |
A modular memory array configuration uses a combinatorial decoding device (decoder), instead of straight buffering, to effect optimal delivery of control and address signals. Each port accessing memory on the array drives a single copy of address and control signals, plus bank select signals, over a shared interface to the decoder. Bank select controls the decoder which drives the address and control to only the accessed bank. Address and control signals to all banks but the accessed bank, are pulled up (inactive) with resistors on the memory array. For N banks, log2 N bank select bits are needed. The decoder device does not need to be clocked and therefore avoids problems associated with selecting between and providing asynchronous or redundant clocks for a multi-ported shared memory with ports independent of and asynchronous to one another. Output glitches on the output control signals are avoided by having the port controller performing a memory access first switch the bank select signals while all other inputs are stable and logically inactive. The bank select value is maintained for the duration of the memory access, while the other inputs may switch. Pin requirements for port controllers and memory array connectors are minimized. Simultaneous switching output noise on both the port controllers and memory array address/control drivers is also minimized.
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