发明名称 |
Data processing system and method for implementing a multi-port memory cell |
摘要 |
The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
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申请公布号 |
US5956286(A) |
申请公布日期 |
1999.09.21 |
申请号 |
US19970958559 |
申请日期 |
1997.10.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LATTIMORE, GEORGE MCNEIL;ROSS, JR., ROBERT ANTHONY;SMADI, MITHKAL MOH'D |
分类号 |
G11C8/16;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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