发明名称 Method of making self-aligned silicide CMOS transistors
摘要 The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a high dose is carried out to dope nitrogen ions into the oxide spacers, the cap silicon nitride and the silicon substrate. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitride doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form shallow source and drain junction.
申请公布号 US5956584(A) 申请公布日期 1999.09.21
申请号 US19980050541 申请日期 1998.03.30
申请人 TEXAS INSTRUMENTS - ACER INCORPORATED 发明人 WU, SHYE-LIN
分类号 H01L21/8238;(IPC1-7):H01L21/823 主分类号 H01L21/8238
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