发明名称 System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline
摘要 A microprocessor includes an instruction fetch unit, a branch prediction unit, and a decode unit. The instruction fetch unit is adapted to retrieve a plurality of program instructions. The program instructions include serialization initiating instructions and branch instructions. The branch prediction unit is adapted to generate branch predictions for the branch instructions, direct the instruction fetch unit to retrieve the program instructions in an order corresponding to the branch predictions, and redirect the instruction fetch unit based on a branch misprediction. The branch prediction unit is further adapted to store a redirect address corresponding to the branch misprediction. The decode unit is adapted to decode the program instructions into microcode. The microcode for each of the serialization initiating instructions includes microcode for writing a serialization address of the program instruction following the serialization initiating instruction in the branch prediction unit as the redirect address and triggering the branch misprediction.
申请公布号 US5954814(A) 申请公布日期 1999.09.21
申请号 US19970994400 申请日期 1997.12.19
申请人 INTEL CORPORATION 发明人 ZAIDI, NAZAR A.;AATRESH, DEEPAK J.;MORRISON, MICHAEL J.
分类号 G06F9/38;(IPC1-7):G06F9/312 主分类号 G06F9/38
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