发明名称 Integrated circuit package and flat plate molding process for integrated circuit package
摘要 An integrated circuit package having a top opening and a cavity, with a chip adhered in the cavity. The top opening has routing strips electrically connecting the top opening with the outer surface. The routing strips are electronically connected to bonding pads located in a central area of the chip. Following assembly of the components, the top opening and the cavity are encapsulated in a molding process. A method is provided for forming a substantially flat integrated circuit package.
申请公布号 SG67384(A1) 申请公布日期 1999.09.21
申请号 SG19970001115 申请日期 1997.04.10
申请人 TEXAS INSTRUMENTS SINGAPORE (PTE) LTD 发明人 CHAN MIN YU;CHAN BOON PEW;ENG KIAN TEN;GOH JING SUA
分类号 H01L23/24;H01L23/495 主分类号 H01L23/24
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