| 摘要 |
Several cache memories are used instead of a continuously large cache memory. Each memory has a defined address range. A plurality of arithmetic units can access a plurality of cache memories due to the fact that the cache memory is selected on the basis of defined addresses. If several arithmetic units access the same cache memory, one of the arithmetic units undergoes arbitration per time unit and is granted the right of access. If the data is not available in the cache memory, bursting occurs when accessing the memory, that is, a plurality of data is written on a complete line of cache memories (CL) in the memory or read from the memory. |
