| 摘要 |
<p>An input-buffered multipoint switch (60) having input channels (62, 64, 66 and 68) and output channels (72, 74, 76 and 78) includes multi-level request buffers (122, 124, 126 and 128), a data multiplexer (130), and a scheduler (132). The switch (60) has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers (160, 162, 164 and 166) for storing data cell transfer requests of different priorities. The multiple request registers (160, 162, 164 and 166) are linked in parallel to the scheduler (132) to allow arbitration among requests of different input channels and different priority levels.</p> |
