Memory cell arrangement

摘要

The arrangement has a semiconductor substrate (2). MOS transistors with a floating gate electrode and a control gate electrode are provided as memory cells in the substrate. Each floating gate electrode (9) is arranged in a groove (7) in a main surface (1) of the substrate. The grooves are bounded by one source/drain region of the MOS transistor. The control gate electrode extends over the gate electrode on the side furthest from the source/drain region. At least part of a channel region of the MOS transistor, between the grooves and a second source/drain region of the MOS transistor, is bounded by the main surface. The control gate electrode is arranged above the part of the channel region bounded by the main surface.