| 摘要 |
<p>An asynchronous mode sigma-delta modulator circuit is usable, for example, at each pixel of a CMOS image sensor. The asynchronous sigma-delta modulator includes a comparator circuit (MND0, MND1, MND2, MPD1, MPD2) whose output switches to indicate when an input signal has reached a predetermined reference level, and a latch circuit (MNL1, MPL2, MPL2) that asserts a pulse signal when the comparator output switches. A pulse capture circuit (MPUL, MRST, MBIT) senses the pulse signal and stores it as a logic value until sampled by a clocked output circuit. Regeneration circuitry (MPS1, MNS1, MPS2, MNS2, MRGN) resets the input signal and the latch circuit after the pulse signal is captured by the pulse capture circuit.</p> |
