Circuit for Synchronisation

摘要

A circuit for aligning the pulses of an input signal (16) with a clock signal (10) has a divide-by-two counter connected to receive the input signal and a D-type flip-flop (2) connected to latch the output of the divide-by-two counter at times determined by the clock signal. The output of the flip-flop (2) is stabilised by sampling again with another flip-flop (3). The resultant signal is combined using an Exclusive-OR gate (12) with a delayed version of itself, provided by a further flip-flop (4) to produce a signal having a pulse for each pulse in the input signal but at times aligned, or synchronised, with the clock signal. <IMAGE>