发明名称 Method for cacheing configuration data of data flow processors and modules with a two- or multidimensional programmable cell structure (fpgas, dpgas or similar)according to a hierarchy
摘要 The method involves one unit managing an associated number equal to some or all of a total number of configurable elements. Reconfiguration requests are sent from the elements to the unit. The unit accepts no further requests and changes during processing; loads yet to be loaded configuration data of earlier requests from an intermediate memory into the configurable element; and converts the current request to a definite identifier or ID. The ID is converted to the address in the unit's memory of the configuration data to be loaded if the data exists in the memory. The data are requested from a superior unit if not present in the unit's memory. The data are loaded if the element can accept them. Data which cannot be accepted are placed in temporary memory. When configuration data have been fully processed, new requests can be accepted, until when the configuration data yet to be loaded from earlier request are loaded into the configurable elements.
申请公布号 AU3137199(A) 申请公布日期 1999.09.15
申请号 AU19990031371 申请日期 1999.02.25
申请人 PACT INFORMATIONSTECHNOLOGIE GMBH 发明人 MARTIN VORBACH;ROBERT MUNCH
分类号 G06F12/08;G06F15/78;G06F15/82;H03K19/173 主分类号 G06F12/08
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