| 摘要 |
There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage (202) coupled to the buffer input node (208). The input stage (202) is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage (204) coupled to the input stage (202). The level shifter stage (204) is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage (206) coupled to the level shifter stage (204). The output stage (206) is configured to output, when the buffer enable signal is enabled, the output signal (210) on the buffer output node responsive to the set of level shifter stage control signals. The voltage range of the output signal is lower than the voltage range of the set of level shifter stage control signals. The output stage (206) decouples the buffer output node from the input stage and the level shifter stage when the buffer enable signal is disabled. <IMAGE> |
