| 摘要 |
An integrated circuit wafer topography monitor is disclosed for sensing mis-processing in the fabrication of integrated circuits. In particular, the monitor senses unacceptable variations in layer planarity resulting from over polishing, over etching, scratches and mishandling. The topography monitor may be placed within the chip active area, the chip kerf area or in unutilized areas of the wafer such as a partial chip site. The monitor is formed when, first a conformal insulator is deposited over the topography of interest. Then, runs of wire are formed in the conformal insulator by a damascene or similar process. The wire runs are formed directly above the topography of interest. A puddle of metal is formed corresponding to any unacceptably non-planar topography. The puddle electrically couples the wires together. This effects a change in the metal runs which may be sensed as an electrical short or change in resistance. The topography of interest is manipulated by design to be representative of corresponding pattern factors found in the active chip area. This then allows the electrically sensed puddles to be indicative of mis-processing to be found in the active chip area.
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