发明名称 |
Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output |
摘要 |
Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.
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申请公布号 |
US5953261(A) |
申请公布日期 |
1999.09.14 |
申请号 |
US19980076887 |
申请日期 |
1998.05.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
FURUTANI, KIYOHIRO;OOISHI, TSUKASA;ASAKURA, MIKIO;HIDAKA, HIDETO;HAMADE, KEI;NAKAOKA, YOSHITO |
分类号 |
G11C11/41;G11C7/10;G11C11/401;G11C29/00;G11C29/14;G11C29/34;G11C29/38;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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