| 摘要 |
A circuit configured to generate an error signal that may be used to disable a loading mechanism (such as a loading mechanism in a wafer sorter). The circuit comprises a wafer sense circuit configured to generate a first pulse in response to a wafer passing a detection point, a pulse generator circuit configured to generate (i) a second pulse in response to a transition (e.g., a positive transition) of the first pulse and (ii) a third pulse in response to a transition (e.g., a negative transition) of the first pulse. An error detection block may be configured to generate an error signal in response to (i) the first pulse, (ii) the second pulse and (iii) the third pulse.
|
