发明名称 |
ESD implantation scheme for 0.35 mu m 3.3V 70A gate oxide process |
摘要 |
A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 mu m technology or less, approaching 0.25 mu m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.
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申请公布号 |
US5953601(A) |
申请公布日期 |
1999.09.14 |
申请号 |
US19980024480 |
申请日期 |
1998.02.17 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
SHIUE, RUEY-YUN;HOU, CHIN-SHAN;WU, YI-HSUN;WU, LIN-JUNE |
分类号 |
H01L21/8238;H01L27/02;H01L27/092;(IPC1-7):H01L21/823;H01L21/823 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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