发明名称 |
Memory device with improved charge storage barrier structure |
摘要 |
A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
|
申请公布号 |
US5952692(A) |
申请公布日期 |
1999.09.14 |
申请号 |
US19970958845 |
申请日期 |
1997.10.28 |
申请人 |
HITACHI, LTD. |
发明人 |
NAKAZATO, KAZUO;ITOH, KIYOO;MIZUTA, HIROSHI;SATO, TOSHIHIKO;SHIMADA, TOSHIKAZU;AHMED, HAROON |
分类号 |
H01L29/78;G11C13/02;G11C16/02;H01L21/28;H01L29/06;H01L29/51;H01L29/772;H01L29/786;H01L29/788;(IPC1-7):H01L29/06 |
主分类号 |
H01L29/78 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|