发明名称 Single-chip memory system having a redundancy judging circuit
摘要 To use both an array of main memory cells and an array of redundant memory cells efficiently during a block writing operation, a memory system for performing the block writing operation includes a bit line activator activating at least one bit line of bit lines of the array of main memory cells and at least one bit line of bit lines of the array of redundant memory cells simultaneously during the block writing operation.
申请公布号 US5951692(A) 申请公布日期 1999.09.14
申请号 US19970788249 申请日期 1997.01.27
申请人 NEC CORPORATION 发明人 KATO, KUNIHIKO
分类号 G11C11/413;G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G06F11/00 主分类号 G11C11/413
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