发明名称 |
Flash memory array and decoding architecture |
摘要 |
A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.
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申请公布号 |
US5953250(A) |
申请公布日期 |
1999.09.14 |
申请号 |
US19980159830 |
申请日期 |
1998.09.24 |
申请人 |
APLUS INTEGRATED CIRCUITS, INC. |
发明人 |
HSU, FU-CHANG;TSAO, HSING-YA;LEE, PETER WUNG |
分类号 |
G11C11/56;G11C16/08;G11C16/14;G11C16/16;G11C16/30;G11C16/34;H01L27/115;(IPC1-7):G11C16/04;G11C16/06 |
主分类号 |
G11C11/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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