发明名称 |
Cacheable interface control registers for high speed data transfer |
摘要 |
A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.
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申请公布号 |
US5951657(A) |
申请公布日期 |
1999.09.14 |
申请号 |
US19970871145 |
申请日期 |
1997.06.09 |
申请人 |
WISCONSIN ALUMNI RESEARCH FOUNDATION |
发明人 |
WOOD, DAVID A.;REINHARDT, STEVEN K.;MUKHERJEE, SHUBHENDU S.;FALSAFI, BABAK;HILL, MARK D.;PFILE, ROBERT W. |
分类号 |
G06F5/10;G06F12/08;(IPC1-7):G06F13/14 |
主分类号 |
G06F5/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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