发明名称
摘要 <p>PURPOSE:To prevent erroneous synchronization due to a pseudo frame synchronization pattern by executing re-locking to the frame synchronization only when error check information exceeds a predetermined value and plural synchronization patterns are in existence in one frame. CONSTITUTION:A frame pulse 29 and a synchronization pulse 21 are inputted to a synchronization pattern counter circuit 8 and the circuit 8 counts a frame synchronization pattern in one frame. When two frame synchronization patterns or over are in existence, a counter circuit (1) 35 and a counter circuit (2) 34 discriminate whether or not two frame patterns or over are in existence in one frame length and provide a plural synchronization pattern existence information pulse 28 as an output to a frame erroneous synchronization discrimination circuit 5. The counter of the circuit 5 counts a dissidence information pulse 22 and discriminates it to be erroneous synchronization when the count exceeds a predetermined value and the pulse 28 is inputted to the circuit 5 and outputs an erroneous synchronization generating pulse 25 to an auxiliary frame counter 6. Upon the receipt of the pulse 25 from the circuit 5, the counter 6 starts frame synchronization hunting.</p>
申请公布号 JP2948058(B2) 申请公布日期 1999.09.13
申请号 JP19930167651 申请日期 1993.07.07
申请人 MITSUBISHI DENKI KK 发明人 KANO TOMOO
分类号 H04J3/06;H04L7/08;(IPC1-7):H04L7/08 主分类号 H04J3/06
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