发明名称 |
Einrichtung zur Datenratenreduktion |
摘要 |
<p>According to the disclosed bit rate reduction apparatus, when quantizing the components transformed in each block, the transformed components in the block are classified into plural sets, and the quantizing width is determined in each classification, and when quantizing with a large quantizing width, the quantizing width of the transformed component belonging to the set of the transformed components less important visually is set larger. <IMAGE></p> |
申请公布号 |
DE69324631(T2) |
申请公布日期 |
1999.09.09 |
申请号 |
DE1993624631T |
申请日期 |
1993.06.11 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO. |
发明人 |
JURI, TATSURO;NISHINO, MASAKAZU |
分类号 |
H04N1/41;G06T9/00;H04N5/926;H04N19/115;H04N19/119;H04N19/126;H04N19/136;H04N19/14;H04N19/176;H04N19/18;H04N19/189;H04N19/196;H04N19/42;H04N19/46;H04N19/60;H04N19/70;H04N19/85;H04N19/86;H04N19/91;(IPC1-7):H04N7/24;H04N7/30;H04N5/92 |
主分类号 |
H04N1/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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