Method for reducing stress in metallization of an integrated circuit

摘要

Stresses commonly induced in dielectrics of integrated circuits manufactured using metal patterning methods, can be reduced by rounding the lower corners associated with features formed as part of the integrated circuit before applying the outer layer. For metal lines patterned by RIE, corners can be rounded using a two-step metal etching process: a first step producing a vertical sidewall and a second step tapering lower portions of the vertical sidewall or producing a tapered spacer along its lower portions. This produces a rounded bottom corner which improves the step coverage of the overlying dielectric, and eliminates the potential for cracks. For metal lines patterned by damascene, corners can be rounded using a two-step trench etching process: a first step producing a vertical sidewall, and a second step producing a tapered sidewall along its lower portions.