| 摘要 |
A data holding circuit is provided that reduces a setup time and hold time when a data is inputted to effectively transmit output data. The data holding circuit includes a latch unit that samples and holds input data, a delay unit that delays a control signal, and a three-phase buffer. The three-phase buffer is enabled based on a delayed control signal from the delay unit to hold data from the latch unit LAT and to transmit output data.
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